One article explains what clock jitter Jitter is and its impact

Clock jitter is a short-term fluctuation or change in the edge of a clock relative to its expected or ideal position. Any source, such as periodic, non periodic, or data dependent sources, may cause the clock edge to deviate from its ideal position. The common sources of these changes include internal device noise (such as thermal noise, flicker noise, etc.), imperfect clock generation circuits, power supply noise, board level defects (such as crosstalk, data dependency interference, reflections caused by poor termination), as well as other board level reasons and system level defects (such as electromagnetic interference sensitivity). Clock jitter can usually be divided into two categories: unbounded or random jitter and bounded or deterministic jitter.

Unbounded or random jitter is caused by random or Gaussian processes in the system. The instantaneous value of this noise source is unbounded and inherent to each system. Deterministic jitter is caused by non random processes and is not inherent in every system. Deterministic jitter can be periodic, such as noise from DC/DC converters, or data dependent, such as inter symbol interference. The deterministic jitter of data dependency can be either uncorrelated or correlated. Although random jitter is difficult to eliminate, deterministic jitter can be reduced through careful system design.

Bounded jitter is represented as peak to peak jitter, while unbounded jitter is represented as root mean square (RMS) jitter. Peak to peak jitter is defined as the difference between the minimum and maximum deviations of the clock edge. When calculating jitter for different sample lengths (10000 samples according to JEDEC standards), the histogram follows a normal or Gaussian distribution. RMS jitter is the value of one standard deviation σ of the histogram. Peak to peak jitter is the distance between the maximum and minimum measurement values on a histogram.

Due to the unbounded nature of random jitter, a maximum bit error rate (BER) is required to convert RMS jitter into peak to peak jitter. The bit error rate is defined as the number of erroneous bits per unit time interval. For example, a bit error rate of 10 to the power of negative 12 indicates that there is at most one bit error in 10 to the power of 12 cycles. In order to convert RMS jitter into peak to peak jitter, a bit error rate multiplier was used based on the assumption of Gaussian noise model. For a bit error rate of 10 to the power of negative 12, the peak to peak jitter is equal to 14.069 times the RMS jitter. For other error rates, the peak to peak jitter can be calculated from the RMS jitter based on the multiplier in the table here.

In serial data communication, data is transmitted from the transmitter to the receiver through a link or physical medium. In some cases, clocks can be transmitted through different links. The speed and efficiency of data transmission depend on many electrical and physical factors. One of the factors is clock jitter. If the clock jitter is too high, the receiver cannot recover data. To evaluate the performance of serial links, data dependent electrical measurements are used to assess high-speed data quality and high-speed transmitter receiver performance.

Eye diagram is a universal tool used for designing and simulating systems, as well as evaluating products with high-speed links. To generate an eye diagram, the input data is repeatedly sampled and continuously displayed on the oscilloscope. If the data link quality is poor or the noise is high, the eye diagram will close and data transmission errors will be high. When the link quality is good, the eye diagram will display clear eye opening.

You can observe the eye diagram of an ideal clock with zero mean frequency error relative to the reference clock. You can also observe the jitter of the reference clock in this eye diagram. Eye diagrams can also perform several key horizontal measurements. Eye width is the most important of these measurements, as it can help you understand how much time the receiver takes to sample a bit within a unit interval.

This measurement is usually taken at the widest part or intersection of the eye chart. Reaching a specific eye width is crucial for passing eye diagram tests, and eye opening limitations are typically described in eye models. Eye width also provides a visual perception of the degree of eye opening from a temporal perspective. The total jitter of the eye diagram can be measured using an oscilloscope and decomposed into its basic components.

As the total jitter increases, the available eye width of the signal decreases and affects how the receiver samples the transmitted data. Eye opening can also be used to estimate the bit error rate of specific eye patterns. Systems with large total jitter often have poor signal performance, may suffer from high bit error rates due to small eye opening, and may not be able to pass eye mode. However, by introducing a high-speed signal conditioner, the amount of jitter in the system can be reduced and some eye width can be restored, which helps to achieve acceptable signal quality performance through eye model testing, increase eye opening, and reduce overall bit error rate.

Edge rates can also be extracted from the eye diagram, which is useful for identifying specific effects that may cause cross region offset, affect eye width, and result in different load effects on transmission lines. When implementing some high-speed data protocols, edge rate can also be another parameter tested in the eye diagram to ensure normal transmitter performance. According to the specifications, edge velocity can be measured in slightly different ways, such as voltage levels of 90%/10%, 80%/20%, or 70%/30%. In the diagram shown here, the measurement points are at a voltage level of 90%/10%.

An analog-to-digital converter (ADC) is used to convert any analog quantity (such as repetitive voltage) into a digital word. In an ideal situation, digital characters should be an accurate representation of the measured analog value. Due to the use of a clock source for sampling input analog signals, noise in the clock source can introduce noise into the sampled values.

Assuming the input is a limited sine signal, the slope of the signal will depend on the sine frequency. The jitter in the clock source is multiplied by the slope of the input signal and converted into noise at the sampler, which in this case is voltage noise. The greater the clock source jitter, the greater the noise at the sampler. The higher the slope of the input signal, the greater the noise at the sampler.

The jitter in the clock source will be limited to the maximum input frequency at a specific signal-to-noise ratio. The diagram here shows a representative curve of the achievable signal-to-noise ratio in ADC under different clock sources. In the effective signal-to-noise ratio formula, σ represents the peak to peak clock jitter.

Tips： Some common questions and answers about jitter

1. Why is random jitter unbounded?

Answer: Random jitter (RJ) refers to temporal changes caused by difficult to predict factors. These factors are usually random and unbounded, so random jitter also exhibits corresponding randomness and boundlessness. Random jitter has no fixed pattern or pattern, and its occurrence time and magnitude are random.

2. Why clock jitter is not a long-term fluctuation of clock edges.

Answer: Clock jitter is the deviation and fluctuation of clock signals in time. It describes the difference between the actual occurrence time of clock signal edges (such as rising or falling edges) and their ideal occurrence time. This difference is usually caused by noise or other interference in the system.

Clock jitter is a short-term variation that does not accumulate over time. This means that jitter may occur within one clock cycle, but at the beginning of the next clock cycle, the impact of jitter will not accumulate into the next cycle.

3. Why is peak to peak jitter not linearly additive for unrelated noise sources.

Answer: Unrelated noise sources mean that these noise sources are independent of each other, meaning that changes in one noise source will not directly affect another noise source.

When multiple unrelated noise sources simultaneously affect the system, each noise source will contribute a certain amount of peak to peak jitter. However, these contributions are not simply linearly additive. Because the jitter distribution of each noise source is independent, their peak to peak jitter is statistically independent of each other.

Statistically, the peak to peak jitter superposition of multiple unrelated noise sources is not simply a linear addition. In fact, the peak to peak jitter after superposition will depend on the jitter distribution, variance, and relative size between each noise source.

4. Why eye diagrams can be used to observe clock jitter.

Answer: Eye Diagram is the result of accumulating and overlaying the bits of the collected serial signal using afterglow. By superimposing signals of multiple bit periods together (usually through the storage function of an oscilloscope), the eye diagram displays the shape, noise, jitter, and other adverse phenomena of the signal. The shape of the overlaid shape looks very similar to the eyes, hence the name eye diagram.

The aperture of the eye diagram (i.e. the width of the "eye" part of the eye diagram) is closely related to jitter and error rate. The larger the eye opening, the smaller the jitter in the signal and the lower the data error rate. On the contrary, if the opening of the eye diagram becomes very small or blurry, it usually indicates that there is too much jitter or noise in the signal, which may lead to decoding errors in the data.

5. Why the signal-to-noise ratio (SNR) of ADC may be limited by clock jitter.

Answer: ADC uses a clock signal to control the sampling time point when converting analog signals into digital signals. The ideal clock signal has a fixed period and edges, but the actual clock signal may experience jitter due to various factors such as noise, interference, circuit instability, etc., resulting in a short-term offset of the clock edges relative to the ideal position.

Clock jitter can cause ADC to sample at incorrect time points. This sampling time offset will introduce sampling errors, manifested as deviations in the sampling values. These deviations manifest as noise in the digital signal, thereby reducing the signal-to-noise ratio of the ADC.

The impact of clock jitter on ADC signal-to-noise ratio can be estimated by the following formula:

−20*log10(2π*fin*tjitter)

Among them, fin is the input signal frequency, and tjiter is the clock jitter.

From the formula, it can be seen that the higher the frequency of the input signal, the greater the clock jitter, and the more significant the decrease in the signal-to-noise ratio of the ADC. This is because high-frequency signals are more sensitive to sampling time offsets, and small jitter can lead to larger sampling errors.

Note: This article is excerpted and reprinted from an article published by the author of Communication RF Veterans