Notes on the Use of RA8900CE Clock Chip

Apr 18,2024
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In the fast-paced modern society, time is becoming increasingly precious. For the electronic design of clocks, high precision and low power consumption have gradually become mainstream. We have a clock display project for a car display screen, which requires the clock's error to be controlled within 1 second per day. To meet this requirement, the frequency deviation PPM of the crystal oscillator must be less than 1/60/60/24 * 1000 * 1000=115.74ppm. For such a high requirement, we have decided to use Epson's in car real-time clock RA8900CE

The previous solution for RTC was to use passive crystal oscillators and achieve time display through software algorithms. When using passive crystal oscillators, CPU support is required, and due to the continuous operation of time counting, the standby power consumption of the entire machine increases. If integrated RA8900CE is used, only the data from the internal registers of RA8900CE needs to be extracted while the host is working, and clock display is achieved through IC communication. This not only reduces standby power consumption, but also reduces software workload, greatly shortening the product development cycle. In addition, the deviation of passive crystal oscillators will change with temperature, which will result in different accuracy of clock display in winter and summer. At its most severe, the deviation of the clock can reach 8.6S per day, and users can easily find that there is a problem with the accuracy of the clock display, which seriously affects the user experience; When using RA8900CE, whether in winter or summer, the clock's daily difference remains within 0.5S, and users will not easily notice any abnormalities in the clock's accuracy, resulting in a better user experience

RA8900CE meets the AEC-Q200 certification standard and is a high-precision DTCXO that integrates 32.768KHz crystal units. It has a frequency deviation of 5ppm over the entire temperature range and a very low operating current of only 0.7uA/3V (Typ.).

Meanwhile, the RA8900CE supports IIC communication up to 400Khz, with interface voltages ranging from 2.5V to 5.5V. The main packaging of RA8900CE is only 2.5mm * 3.2mm. Small packaging is conducive to PCB wiring, making it convenient for us to place RA8900CE near the MCU, greatly reducing the difficulty of PCB wiring. Therefore, it not only meets the requirements of crystal oscillators but also reduces the difficulty of PCB wiring, which can be said to be killing two birds with one stone.

After adding the RA8900CE chip, we found that after the sample was first powered on, the DAB chip could not communicate with the MCU normally. The circuit diagram of the sample is shown in the following figure:

Figure 1: Clock display circuit diagram of car display screen

Problem analysis and resolution

The sample is powered on for the first time, and the DAB chip cannot communicate with the MCU normally. This is a challenging question, and in order to explore the reasons, we adopt an exclusion method of thinking and analyze it as follows:

Figure 2: Problem Analysis

Firstly, lock the module that caused the problem. We first confirm the power on timing of the DAB, as shown in Figure 3. The DAB chip has a requirement for the power on timing, that is, the interface power supply DVDDIO must be powered on after the main power supply VBAT. However, after testing, we found that DVDDIO was powered on earlier than VBAT, resulting in abnormal DAB communication. The cause of DAB communication abnormalities has been identified, but why is the power on timing not met?

The DAB power supply we designed is shown in Figure 3, which controls 5VSW and 3.3VSW through MCU to ensure that 5VSW and 3.3VSW are powered on in advance. The theoretical design fully meets the requirements of DAB power on timing. But why is there a significant difference between the actual situation and the theoretical design?

Figure 3: DAB power on timing

By measuring the power supply timing, we ultimately found that it was due to the addition of the RA8900CE chip, which caused power supply cascading during the initial power on stage. The 3.3VSW power supply followed the 3.3VMEM to power on earlier, resulting in non-compliance with the DAB power on timing requirements.

The internal circuit of RA8900CE is shown in Figure 4. In order to prevent power failure during 3.3VSW, we set the register address of RA8900 to VDETOFF, SWOFF=(1.1). This setting ensures that the switch between the VDD and VBAT inside RA8900CE is always turned off. But when the machine is first powered on, the register of RA8900CE is set to the default value, and our software can only set the register address of RA8900CE to VDETOFF after the MCU is up SWOFF=(1.1). This will result in a period of time when VBAT and VDD are directly connected, causing the 3.3VSW power supply to follow the 3.3VMEM to power on earlier, leading to abnormal communication between DAB and MCU.

Figure 4: Internal circuit of RA8900CE

Knowing the root cause of the problem makes it easy to find a solution. Due to the maximum current consumed by the VDD power supply during RA8900CE operation being 1.45uA, the current consumption is very small. Therefore, we have decided to adopt the solution of sharing the same power supply for VDD and VBAT, that is, using a 3.3VMEM power supply for both. This fundamentally solves the problem of serial power supply, thereby ensuring the power on timing of DAB and solving the problem of communication failure between DAB and MCU.